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authorarchitW <archit2x3@hotmail.com>2019-12-30 21:05:53 +0530
committerAlban Vidal <zordhak@debian.org>2020-01-02 18:56:50 +0100
commit9c2d7ccd8a918600f491847183ae57109b0bd9ab (patch)
tree1158c07f806ea098dd2337117f61edee22977533 /swedish/ports
parentbdd691399182ea5bd043995e363a8f7d5f2121c0 (diff)
Updated riscv.org link to https
Diffstat (limited to 'swedish/ports')
-rw-r--r--swedish/ports/index.wml2
1 files changed, 1 insertions, 1 deletions
diff --git a/swedish/ports/index.wml b/swedish/ports/index.wml
index cc8b0ab08e4..649f2a56ba0 100644
--- a/swedish/ports/index.wml
+++ b/swedish/ports/index.wml
@@ -318,7 +318,7 @@ lågenergi FreeScale och IBM "e500"-CPUer.
<tr>
<td><a href="https://wiki.debian.org/RISC-V">riscv64</a></td>
<td>RISC-V (64-bitars little endian-läge)</td>
-<td>Port for <a href="http://riscv.org/">RISC-V</a>, en fri/öppen ISA, specifikt 64-bitars little-endian-varianten.</td>
+<td>Port for <a href="https://riscv.org/">RISC-V</a>, en fri/öppen ISA, specifikt 64-bitars little-endian-varianten.</td>
<td>under utveckling</td>
</tr>

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