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authorarchitW <archit2x3@hotmail.com>2019-12-30 21:05:53 +0530
committerAlban Vidal <zordhak@debian.org>2020-01-02 18:56:50 +0100
commit9c2d7ccd8a918600f491847183ae57109b0bd9ab (patch)
tree1158c07f806ea098dd2337117f61edee22977533 /italian/ports
parentbdd691399182ea5bd043995e363a8f7d5f2121c0 (diff)
Updated riscv.org link to https
Diffstat (limited to 'italian/ports')
-rw-r--r--italian/ports/index.wml2
1 files changed, 1 insertions, 1 deletions
diff --git a/italian/ports/index.wml b/italian/ports/index.wml
index 88e997aaca4..973793863d7 100644
--- a/italian/ports/index.wml
+++ b/italian/ports/index.wml
@@ -325,7 +325,7 @@ a basso consumo FreeScale a 32-bit e IBM <q>e500</q>.
<tr>
<td><a href="https://wiki.debian.org/RISC-V">riscv64</a></td>
<td>RISC-V (64-bit little endian)</td>
-<td>Port per <a href="http://riscv.org/">RISC-V</a>, un ISA libero/aperto,
+<td>Port per <a href="https://riscv.org/">RISC-V</a>, un ISA libero/aperto,
in particolare per la variante 64-bit little-endian.</td>
<td>in preparazione</td>
</tr>

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